Given that NOT, 2-input AND/OR gates have delays of 1 ns, what will be the maximum delay of a
2x1 multiplexer circuit?
Note: if the answer is 1 ns, write 1.
A published solution is not available for this question yet.
Consider the circuit consisting of three D flipflops and one NAND gate as shown below. The initial
states are Q1=1, Q2=0, and Q3=1. What is the output after (Q1,Q2,Q3) after 5 clock pulse?
Note: If answer is Q1=0, Q2=0, Q3=0, then write 000
A published solution is not available for this question yet.
A modern RISC processor contains 32 registers in its general-purpose register file. The Arithmetic
Logic Unit (ALU) of the processor is capable of executing 8 distinct operations, which include
standard arithmetic and logical functions.
What is the
number of bits required by a
instruction to perform a
bitwise
operation between two source operands located in the register file, and store the
computational result back into a designated destination register?
A published solution is not available for this question yet.
In the circuit shown below, D1 and D2 are positive triggered D flipflops, x1 and x2 are inputs of D1
and D2 flipflop.
Choose the correct timing diagram of the output Y.
Consider a gated D-Latch constructed using NAND gates. The initial input (at 0 ns) is D = 1, and the
write enable is high. The write enable toggles between high and low every 5 ns. The input D
changes from 0 to 1 and from 1 to 0 every 6 seconds. What will be the output Q after 22 ns?
A published solution is not available for this question yet.