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Computer Systems Design · End Term · Sep 2025 · AN

Computer Systems Design · End Term · Sep 2025 AN

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Questions and published explanations below are available without starting a test. Some questions may not have a published solution yet.

0 / 20 published solutions

Question 2 MCQ · 1.0 marks

A multiplexer is a combinational circuit that selects one input from multiple inputs and forwards it to a single output.
6406536036618.
True
6406536036619.
False

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Question 3 MCQ · 1.0 marks

A JK flip-flop cannot store information without a continuous clock input.
6406536036620.
True
6406536036621.
False

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Question 4 MCQ · 1.0 marks

In a 4-bit system, the two's complement of a binary number 1010 can be represented as -6.
6406536036622.
True
6406536036623.
False

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Question 5 MCQ · 1.0 marks

A decoder performs the inverse operation of a multiplexer.
6406536036624.
True
6406536036625.
False

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Question 6 MCQ · 1.0 marks

According to Moore's Law, the size of transistors on an integrated circuit doubles approximately every two years.
6406536036626.
True
6406536036627.
False

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Question 7 NAT · 3.0 marks

Using 2's complement method, evaluate
Source diagram or notation
where
Source diagram or notation
and
Source diagram or notation
. Give the answer in 8-bit binary format.

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Question 8 MCQ · 3.0 marks

Source diagram or notation
6406536036629.
OR,NAND
6406536036630.
OR,NOR
6406536036631.
AND,NOR
6406536036632.
AND,NAND
6406536036633.
None of these

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Question 9 NAT · 3.0 marks

Source diagram or notation

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Question 10 NAT · 3.0 marks

Source diagram or notation

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Question 11 NAT · 3.0 marks

Given that NOT, 2-input AND/OR gates have delays of 1 ns, what will be the maximum delay of a 2x1 multiplexer circuit? Note: if the answer is 1 ns, write 1.

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Question 12 NAT · 3.0 marks

Consider the circuit consisting of three D flipflops and one NAND gate as shown below. The initial states are Q1=1, Q2=0, and Q3=1. What is the output after (Q1,Q2,Q3) after 5 clock pulse?
Source diagram or notation
Note: If answer is Q1=0, Q2=0, Q3=0, then write 000

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Question 13 NAT · 3.0 marks

Source diagram or notation

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Question 14 SHORT_TEXT · 3.0 marks

Source diagram or notation

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Question 15 NAT · 3.0 marks

Consider the circuit diagram as shown below. Assuming it was initially cleared to 0, state the output(Y) for the next 4 clock pulses.
Source diagram or notation

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Question 16 MCQ · 3.0 marks

Source diagram or notation
6406536036641.Source diagram or notation
6406536036642.Source diagram or notation
6406536036643.Source diagram or notation
6406536036644.Source diagram or notation

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Question 17 NAT · 3.0 marks

A modern RISC processor contains 32 registers in its general-purpose register file. The Arithmetic Logic Unit (ALU) of the processor is capable of executing 8 distinct operations, which include standard arithmetic and logical functions. What is the
Source diagram or notation
number of bits required by a
Source diagram or notation
instruction to perform a bitwise
Source diagram or notation
operation between two source operands located in the register file, and store the computational result back into a designated destination register?

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Question 18 SHORT_TEXT · 3.0 marks

Source diagram or notation

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Question 19 MCQ · 3.0 marks

In the circuit shown below, D1 and D2 are positive triggered D flipflops, x1 and x2 are inputs of D1 and D2 flipflop. Choose the correct timing diagram of the output Y.
Source diagram or notation
6406536036647.Source diagram or notation
6406536036648.Source diagram or notation
6406536036649.Source diagram or notation
6406536036650.Source diagram or notation
6406536036651.
None of these

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Question 20 NAT · 3.0 marks

Source diagram or notation

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Question 21 NAT · 3.0 marks

Consider a gated D-Latch constructed using NAND gates. The initial input (at 0 ns) is D = 1, and the write enable is high. The write enable toggles between high and low every 5 ns. The input D changes from 0 to 1 and from 1 to 0 every 6 seconds. What will be the output Q after 22 ns?

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