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cs3031_2025T3_ET_FN.pdf

Computer Systems Design · End Term · Sep 2025 FN

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Questions and published explanations below are available without starting a test. Some questions may not have a published solution yet.

Question 2 MCQ · 1.0 marks

A multiplexer is a combinational circuit that selects one input from multiple inputs and forwards it to a single output.
  1. True
  2. False

A published solution is not available for this question yet.

Question 3 MCQ · 1.0 marks

A JK flip-flop cannot store information without a continuous clock input.
  1. True
  2. False

A published solution is not available for this question yet.

Question 4 MCQ · 1.0 marks

In a 4-bit system, the two's complement of a binary number 1010 can be represented as -6.
  1. True
  2. False

A published solution is not available for this question yet.

Question 5 MCQ · 1.0 marks

A decoder performs the inverse operation of a multiplexer.
  1. True
  2. False

A published solution is not available for this question yet.

Question 6 MCQ · 1.0 marks

According to Moore's Law, the size of transistors on an integrated circuit doubles approximately every two years.
  1. True
  2. False

A published solution is not available for this question yet.

Question 7 NAT · 3.0 marks

[[IMAGE:3bdb9b8bc7aa16f0_3_2]]
Source diagram or notation

    A published solution is not available for this question yet.

    Question 8 MCQ · 3.0 marks

    [[IMAGE:3bdb9b8bc7aa16f0_4_3]]
    Source diagram or notation
    1. OR, NOR
    2. OR, NAND
    3. AND, NAND
    4. AND, NOR
    5. None of these

    A published solution is not available for this question yet.

    Question 9 NAT · 3.0 marks

    [[IMAGE:3bdb9b8bc7aa16f0_5_4]]
    Source diagram or notation

      A published solution is not available for this question yet.

      Question 10 NAT · 3.0 marks

      Given that NOT, 2-input AND/OR gates have delays of 1 ns, what will be the maximum delay of a 2x1 multiplexer circuit? Note: if the answer is 1 ns, write 1.

        A published solution is not available for this question yet.

        Question 11 NAT · 3.0 marks

        Consider the circuit consisting of three D flipflops and one NAND gate as shown below. The initial states are Q1=1, Q2=0, and Q3=1. What is the output after (Q1,Q2,Q3) after 4 clock pulse? [[IMAGE:3bdb9b8bc7aa16f0_6_5]] Note: If answer if Q1=0, Q2=0,Q3=0, then write 000
        Source diagram or notation

          A published solution is not available for this question yet.

          Question 12 NAT · 3.0 marks

          A processor uses the following control word format: [[IMAGE:3bdb9b8bc7aa16f0_6_6]] How many registers can be addressed in the register bank?
          Source diagram or notation

            A published solution is not available for this question yet.

            Question 13 NAT · 3.0 marks

            Using 2's complement method, evaluate [[IMAGE:3bdb9b8bc7aa16f0_7_7]] where [[IMAGE:3bdb9b8bc7aa16f0_7_8]] and [[IMAGE:3bdb9b8bc7aa16f0_7_9]] . Give the answer in 8-bit binary format.
            Source diagram or notationSource diagram or notationSource diagram or notation

              A published solution is not available for this question yet.

              Question 14 MCQ · 3.0 marks

              Choose the correct truth table according to the given Boolean expression: [[IMAGE:3bdb9b8bc7aa16f0_8_10]]
              Source diagram or notation
              1. [[IMAGE:3bdb9b8bc7aa16f0_8_11]]
                Source diagram or notation
              2. [[IMAGE:3bdb9b8bc7aa16f0_8_12]]
                Source diagram or notation
              3. [[IMAGE:3bdb9b8bc7aa16f0_8_13]]
                Source diagram or notation
              4. [[IMAGE:3bdb9b8bc7aa16f0_9_14]]
                Source diagram or notation

              A published solution is not available for this question yet.

              Question 15 SHORT_TEXT · 3.0 marks

              Consider a common bus architecture containing memory and three registers: A, B, and C. The control word format is shown below. [[IMAGE:3bdb9b8bc7aa16f0_9_15]] What would be the control word if you intend to perform a register transfer from register A to register B? **Note:** Provide your answer in hexadecimal format (e.g., 0x3A).
              Source diagram or notation

                A published solution is not available for this question yet.

                Question 16 NAT · 3.0 marks

                A modern RISC processor contains 64 registers in its general-purpose register file. The Arithmetic Logic Unit (ALU) of the processor is capable of executing 16 distinct operations, which include standard arithmetic and logical functions. What is the [[IMAGE:3bdb9b8bc7aa16f0_10_16]] number of bits required by a [[IMAGE:3bdb9b8bc7aa16f0_10_17]] instruction to perform a bitwise [[IMAGE:3bdb9b8bc7aa16f0_10_18]] operation between two source operands located in the register file, and store the computational result back into a designated destination register?
                Source diagram or notationSource diagram or notationSource diagram or notation

                  A published solution is not available for this question yet.

                  Question 17 SHORT_TEXT · 3.0 marks

                  [[IMAGE:3bdb9b8bc7aa16f0_10_19]]
                  Source diagram or notation

                    A published solution is not available for this question yet.

                    Question 18 NAT · 3.0 marks

                    Consider a gated D-Latch constructed using NAND gates. The initial input (at 0 ns) is D = 1, and the write enable is high. The write enable toggles between high and low every 5 ns. The input D changes from 0 to 1 and from 1 to 0 every 6 seconds. What will be the output Q after 16 ns?

                      A published solution is not available for this question yet.

                      Question 19 MCQ · 3.0 marks

                      In the circuit shown below, D1 and D2 are positive edge triggered D flipflops, x1 and x2 are inputs of D1 and D2 flipflop. Choose the correct timing diagram of the output Y. [[IMAGE:3bdb9b8bc7aa16f0_12_20]]
                      Source diagram or notation
                      1. [[IMAGE:3bdb9b8bc7aa16f0_12_21]]
                        Source diagram or notation
                      2. [[IMAGE:3bdb9b8bc7aa16f0_12_22]]
                        Source diagram or notation
                      3. [[IMAGE:3bdb9b8bc7aa16f0_13_23]]
                        Source diagram or notation
                      4. [[IMAGE:3bdb9b8bc7aa16f0_13_24]]
                        Source diagram or notation
                      5. None of these

                      A published solution is not available for this question yet.

                      Question 20 NAT · 3.0 marks

                      Consider the circuit diagram as shown below. Assuming it was initially cleared to 0, state the output(Y) for the next 4 clock pulses. [[IMAGE:3bdb9b8bc7aa16f0_14_25]]
                      Source diagram or notation

                        A published solution is not available for this question yet.

                        Question 21 NAT · 3.0 marks

                        Consider the function given below: [[IMAGE:3bdb9b8bc7aa16f0_14_26]] If we want to implement the minimized expression using only 2-input NAND gates, what is the minimum number of NAND gates required?
                        Source diagram or notation

                          A published solution is not available for this question yet.