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cs3031_2025T3_Q2_NA.pdf

Computer Systems Design · Quiz 2 · Sep 2025

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Questions and published explanations below are available without starting a test. Some questions may not have a published solution yet.

Question 68 MCQ · 1.0 marks

Sequential circuit output depends only on current input while combinational circuit output depends on current and past input values
  1. * True
  2. ¥ False

A published solution is not available for this question yet.

Question 69 MCQ · 1.0 marks

In a gated D-Latch, when write enable is 0, the latch holds its previous output regardless of the input.
  1. ¥ True
  2. * False

A published solution is not available for this question yet.

Question 70 MCQ · 1.0 marks

In aJ-K flip flop, when J=1 and K=1, it toggles the flipflop’s state.
  1. ¥ True
  2. * False

A published solution is not available for this question yet.

Question 74 MCQ · 5.0 marks

Consider the circuit diagram below with two D-flipflops, one XNOR gate and one NAND gate. Determine the correct sequence of output states. Note: initially D1 is in the set and D2 is in the reset state LSB
  1. * 011 — 110 - 010
  2. * O11 — O11 — 001 6406535942609, v O11 + 111 — 000
  3. * 011 — 110 — 000 6406535942611, * None of these

A published solution is not available for this question yet.

Question 75 MCQ · 6.0 marks

Consider the circuit shown below. Choose the valid timing diagram that corresponds to the circuit. Y D flip-flop Figure 1: Circuit Diagram
  1. * CLK a | \ ae 2)
  2. * CLK | dp | a a (ae Y Pox. i
  3. * CLK | | | a a ae { CANCOCIOCOAAIDOCNA Zt Y Nf an,
  4. * N f th 6406535942606, # One OF these

A published solution is not available for this question yet.

Question 76 MCQ · 6.0 marks

Consider the following circuit. Logic ox—> afp— Figure 2: Logic Circuit Given the truth table below, determine the equation for logic in terms of A, B, and Q,. ATBY Quit 0/0} Qn O11) O 1/0] 1{1] Qn
  1. * A(B ® Qn)
  2. Y (A® BSQn) t 6406535042616, # None of these

A published solution is not available for this question yet.

Question 77 NAT · 6.0 marks

Answer the following question based on given timing diagram. Output(Y) Figure 3: Timing Diagram Given that we only have 2-input NOR gates are available, what is the minimum number of NOR gates required to represent a circuit whose output timing diagram matches as Y?

    A published solution is not available for this question yet.

    Question 78 NAT · 6.0 marks

    A positive-edge triggered D flip-flop is initially in the reset state (Q = 0). The input signal D and the clock signal are shown below: Clock period = 10ns D=1 from t=12ns to t=22ns,t=31 nsto t = 35 ns, t = 40 ns to t=45 ns, and D=0 otherwise. Assume the flip-flop samples D at the rising edge of the clock, and each rising edge occurs at t = 0, 10,20,30,40,... ns. What will be the decimal equivalent of the 4-bit output sequence Q observed at t = 10,20, 30,40 ns?

      A published solution is not available for this question yet.

      Question 79 NAT · 6.0 marks

      Consider the circuit diagram using J-K flipflop as shown below. Assuming it is initially cleared to 0, state the output Y for the next 4 clock pulses.

        A published solution is not available for this question yet.