cs3031_2026T2_Q2_NA.pdf

Computer Systems Design · Quiz 2 · May 2026

Questions and published explanations below are available without starting a test. Some questions may not have a published solution yet.

Question 2 MCQ · 1.0 marks

In a J-K flipflop, when J = 1 and K = 1, it toggles the flipflop’s state.

TRUE
FALSE

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Question 3 MCQ · 1.0 marks

A multiplexer is a digital circuit that selects one of the several input signals and forwards it to a single output line.

TRUE
FALSE

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Question 4 MCQ · 1.0 marks

In a NAND-based gated D latch, when the write enable input is 0, it denotes the **Memory Hold** state.

TRUE
FALSE

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Question 5 MCQ · 1.0 marks

In a positive-edge-triggered D flipflop, if the D input is 1 and the clock signal transitions from low to high, Q output is 1.

TRUE
FALSE

A published solution is not available for this question yet.

Question 6 MCQ · 1.0 marks

Sequential circuits do not utilize feedback loops, while combinational circuits do.

TRUE
FALSE

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Question 7 NAT · 5.0 marks

[[IMAGE:8eec41e27e72a214_3_2]]

A published solution is not available for this question yet.

Question 8 NAT · 5.0 marks

Consider a gated D-Latch constructed using NAND gates. The initial input (at t=0 ns) is D=1, and the write enable (WE) signal is high. The write enable toggles between high and low every 5ns, while the input D changes from 1 to 0 and back to 1 every 8ns. What will be the output Q after 24ns?

A published solution is not available for this question yet.

Question 9 NAT · 5.0 marks

Consider the J-K flipflop circuit shown below. Assuming the flipflop is initially set to 1, what will be the output sequence Y for the next four clock pulses? [[IMAGE:8eec41e27e72a214_4_3]]

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Question 10 NAT · 5.0 marks

Consider the circuit consisting of three D flipflops and one NAND gate as shown below. The initial states are Q1=0, Q2=0, and Q3=0. What is the output after (Q1,Q2,Q3) after 5th clock pulse? [[IMAGE:8eec41e27e72a214_5_4]]

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Question 11 MCQ · 4.0 marks

[[IMAGE:8eec41e27e72a214_5_5]]

F = [[IMAGE:8eec41e27e72a214_5_6]]
F = [[IMAGE:8eec41e27e72a214_5_7]]
F = [[IMAGE:8eec41e27e72a214_5_8]]
None of these

A published solution is not available for this question yet.

Question 12 NAT · 3.0 marks

If we want to design the given minterm F= [[IMAGE:8eec41e27e72a214_6_9]] using 3-input NAND gates, what is the minimum number of NAND gates required?

A published solution is not available for this question yet.

Question 13 NAT · 3.0 marks

If we want to design the given minterm F= [[IMAGE:8eec41e27e72a214_6_10]] using 2:1 multiplexers, what is the minimum number of multiplexers required?

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Question 14 MCQ · 5.0 marks

Choose the correct option:

[[IMAGE:8eec41e27e72a214_6_11]]
[[IMAGE:8eec41e27e72a214_6_12]]
[[IMAGE:8eec41e27e72a214_7_13]]
[[IMAGE:8eec41e27e72a214_7_14]]

A published solution is not available for this question yet.

Question 15 MCQ · 5.0 marks

For the circuit shown in Figure 1, D1 and D2 are positive-edge-triggered D flip-flops with inputs x1 and x2 respectively, and their outputs Q1, Q2 feed into an XOR gate to produce Y . Which of the following correctly gives the Boolean expression for Y and the condition under which Y = 1? [[IMAGE:8eec41e27e72a214_7_15]]

Y = Q1 · Q2; Y = 1 whenever x1 = x2 = 1 at the previous rising edge of CLK
Y = Q1 ⊕ Q2; Y = 1 whenever x1 [[IMAGE:8eec41e27e72a214_7_16]] x2 at the previous rising edge of CLK
Y = Q1 + Q2; Y = 1 whenever either x1 or x2 was 1 at the previous rising edge of CLK
Y = [[IMAGE:8eec41e27e72a214_7_17]] ; Y = 1 whenever x1 = x2 at the previous rising edge of CLK

A published solution is not available for this question yet.

Question 16 MCQ · 5.0 marks

We want to implement a circuit that outputs the sequence changing from 00 → 11 → 10 → 01 → 00 using J-K flipflops, as shown in the figure below. What should be the values of J1, K1, J2 and K2? [[IMAGE:8eec41e27e72a214_8_18]]

J1=Q2, K1=Q2, J2=1, K2=1
J1=Q2, K1=Q2, J2= [[IMAGE:8eec41e27e72a214_8_19]] , K2= [[IMAGE:8eec41e27e72a214_8_20]]
J1=Q2, K1= [[IMAGE:8eec41e27e72a214_8_21]] , J2=Q1, K2= [[IMAGE:8eec41e27e72a214_8_22]]
J1= [[IMAGE:8eec41e27e72a214_8_23]] , K1= [[IMAGE:8eec41e27e72a214_8_24]] , J2= [[IMAGE:8eec41e27e72a214_8_25]] , K2=1
None of these

A published solution is not available for this question yet.